ASIC Verification Engineer Resume
Here is the ASIC Verification Engineer Resume example:
3229 New Street
Beaver Creek, OR 97004
[email]Job Objective Seeking an ASIC Verification Engineer position that enables me to utilize my skills within the field to make a positive contribution to the company.
Summary of Qualifications:
- Extensive experience in Design Verification
- In-depth knowledge of ASIC Design Flow, System Verilog, Vera, SystemC, HDL, constrained verification
- Profound knowledge of enforcing test cases, SOC simulation and verification methodology
- Huge knowledge of outlining test and coverage plans, ASIC verification field and debugging firmware
- Skilled in in writing test plans, coverage plans, debugging RTL and Gate-Level netlists
- Solid understanding of developing system level test cases and ASIC Design Flow
- Strong communication skills
ASIC Verification Engineer, August 2005 – Present
R & R Staffing, Inc., Beaver Creek, OR
- Managed RTL design verification.
- Outlined functional verification plans.
- Established verification settings and originator test generators.
- Assisted RTL design engineers.
- Managed design verification on varied functional blocks.
- Handled verification plans.
- Maintained functional specification of complex networking and storage.
BS Degree in Computer Engineering, Southwest Wisconsin Technical College, Fennimore, WI
444 N Michigan Ave
San Francisco, CA 94102
Objective To obtain an ASIC Verification Engineer position that will utilize my skills and experience in engineering.
- Strong knowledge of Ethernet protocols.
- Sound knowledge of FPGA design flow.
- Well-versed with various networking technologies.
- Familiar with VHDL, Verilog, C and C++, Matlab, system verilog and assembly language.
- ASIC Verification Engineer, 2006 to till date
- Kabira Technologies, Inc., CA
- Designed, analyzed and tested microcontroller operated digital and analog electronics.
- Developed, designed and verified the electronics hardware design of the system.
- Planned and created design specifications, chip level architecture, FPGA design, code, simulation and synthesis.
- Designed and specified micro-architecture.
M.S in Electrical Engineering, 2006
University of North Carolina, Chapel Hill
B.S in Electronics Engineering, 2004
Pennsylvania State University, University Park
- 1File Count
- March 1, 2021Create Date
- March 1, 2021Last Updated